An integrated circuit (IC) is fabricated according to a set of layouts usable to form corresponding masks for selectively forming or removing various layers of features, such as active regions, gate electrodes, various layers of isolation structures, and/or various layers of conductive structures. Many fabrication processes are available to increase the spatial resolution of various layers of features and thus allow layout patterns to have a finer spatial resolution requirement in a corresponding layout. Some approaches usable for increasing the spatial resolution include using one or more fabrication processes such as ultraviolet lithography, extreme ultraviolet lithography, electron-beam lithography, and/or multiple-patterning. However, in many applications, a fabrication process offering a finer spatial resolution often comes with a higher cost, lower yield, and/or longer processing time. Having every layer of features of an IC fabricated by processes offering the same spatial resolution is not always economically feasible.